Sony UniLink (Sony Bus)

Here is a great UniLink project based on PIC microcontroller.
Note that this information copyright by Sony

Sony UniLink Sources:
UniLink Guidebook9-956-741-21
CDX-U500 Training ManualA-114792-01

Take a look at the XA-107 and XA-300 Unilink AUX input device:
UniLink Connector

Pin Out:

  1. Ready (on older systems)
  2. Reset (from master)
  3. SIRCS (decoded by master then may issue UniLink commands)
  4. Clock (from master)
  5. Data (bidirectional 5V TTL I/O)
  6. Bus On (from master, cascaded to other slaves)
  7. Battery/Backup Power (+12V 2A max)
  8. Ground (for communications)

  1. Ready
    Use Unknown. Not Connected.
  2. Reset (from master)
    Reset signal sent to slaves. Slaves can not send resets to master. LOW going pulse signals the system reset.
  3. SIRCS (decoded by master then may issue UniLink commands)
    This line is used by the master to receive SIRCS data (Serial InferRed Control System, also known as Control-S). The master may understand the request and then send UniLink control messages. Most slaves to not use this becase they are not in range of the user and/or don't understand SIRCS.
  4. Clock (from master)
    Bus clock signal generated from the master for all bus signals.
  5. Data (bidirectional I/O and Request)
    When the bus is active it may be idle or active. When idle the bus appears as a square wave with a period of 16ms (8ms low and 8ms high). When the data bus is active and data is flowing the pulse width of the square wave will change length depending on the data word length (see secton on data communication). Master can send communications at any time. Slaves must send a request for polling. When the master polls slaves can respond.
  6. Bus On (from master, cascade to other slaves)
    Bus on can only be activated from the master (but the slave can request a wakeup). When the bus is off, it is in 'sleep' mode and there is no data communications. High=ON. Low=OFF
  7. Battery/Backup Power (12V 2A)
  8. Ground (for communications)


Data Format

Idledataline is low for 8ms then high for 8ms
short word11ms
medium word16ms
long word21ms

Line is stable 3ms before first byte (included in total time)

Word Length: (each byte is 8 bits)
Short Word6 bytes
Middle Word11 bytes
Long Word16 bytes

Each word contains:

  1. Two address bytes
    RAD (to/receiver address)
    TAD (from/transmitter address)
    Both are 4bits Group and 4bits Member
  2. Two Operation data bytes (OP bytes)
  3. Parity Byte
  4. Additional Data and Parity bytes
    Short WordNo extra data bytesNo Second Parity
    Middle Word6 data bytesSecond Parity Byte
    Long Word11 data bytesSecond Parity Byte
  5. Error Byte
    To indicate failure of function
    This byte is optional and only transmitted if there is an error code (FF=no error?)


10Master (head CPU)
18Entire System (Broadcast)
30CD Group (Broadcast)

Short Word OP
01 02Anyone?
01 04Appoint End

Error Byte Codes
FFNo Error (?)

Other Images: